(1) Field of the Invention
The present invention relates to a motion circuit which is composed of polycrystalline silicon semiconductor layers and has a logical circuit performing established operations with a normal phase and a reverse phase clock signal, and more specifically, to a motion circuit comprising a shift register such as a transfer gate type shift register, which shifts an entered start signal in time with a normal phase and a reverse phase clock signal.
The present invention also relates to an on-board driver circuit for a liquid crystal display panel employing the motion circuit.
(2) Description of the Prior Art
Driver circuits displaying images on a matrix display panel have been required to perform higher-speed operations as the display panel has a larger screen and higher resolution. To meet the demands, a driver circuit unit is generally made of a high-speed single crystalline silicon LSI and connected to a display panel from outside.
FIG. 25 is a circuit diagram showing the structure of a general driver circuit for a display panel. The diagram shows an external timing circuit 41, a scanning side driver circuit 42, an image signal side driver circuit 43, and a matrix display panel 44. The scanning side driver circuit 42 mainly consists of a shift register and a buffer. The image signal side driver circuit 43 comprises, when its image signal source is analog, a shift register, a buffer, and an analog switch, and comprises, if the image signal source is digital, a shift register, a latch, and a D/A converter as shown in FIG. 25. As for circuit operations, the external timing circuit 41 supplies the shift registers contained in the scanning side driver circuit 42 and the image signal side driver circuit 43 with start signals and clock signals. These two driver circuits select pixels on arbitrary positions on the display panel, thereby driving the pixel transistors ON so as to write image signals sequentially. The clock signals supplied from the external timing circuit 41 to the driver circuits 42 and 43 are single phase clock signals from which internal inverters 50 and 51 generate reverse phase clock signals.
On the other hand, it has been suggested that a display unit and a driver circuit should be formed on the same substrate of a display panel by employing polycrystalline silicon thin-film transistors. As shown in FIG. 26, the display panel 49 contains a scanning side driver circuit 46 and an image signal side driver circuit 47, and directly enters the output signals of the external timing circuit 45. The on-board driver circuit operates basically in the same manner as the driver circuit composed of single crystalline silicon; the driver circuit selects arbitrary pixels on the display unit 48, thereby driving the pixel registers ON as to write image signals sequentially. However, polycrystalline silicon is inferior to single crystalline silicon in the speed of transmitting clock signals to the driver circuits, so a normal phase and a reverse phase clock signal have to be entered instead of a single phase clock signal.
The reason for this is as follows. In the driver circuits 42 and 43 composed of single crystalline silicon, a delay time caused when single phase clock signals entered from the external timing circuit 41 are logical-reversed in the internal inverters 50 and 51 so as to generate reverse clock signals is so small that the phase difference (hereinafter referred to as skew) between the normal phase and the reverse phase clock signal causes no serious problems. In contrast, the use of polycrystalline silicon causes a longer delay time in the inverters, so that the generation of the normal phase and the reverse phase clock signal from the single clock signal might cause malfunctions of the driver circuit due to the skew between the normal phase and the reverse phase clock signal. In other words, a large skew between the normal phase and the reverse phase clock signal causes a so called fail phenomenon according to which the shift registers cannot latch signals at each stage sent from a previous stage, which prevents signals normally shifted in time from being outputted from the shift registers. As a result, the driver circuit causes malfunctions. To avoid the trouble, conventional driver circuits composed of polycrystalline silicon semiconductor layers are operated with a normal phase and a reverse phase clock signal having a small skew, which are directly supplied from an external timing circuit.
In the on-board driver circuit shown in FIG. 25, supplying a normal phase and a reverse phase clock signal from the external circuit 41 requires two clock signal lines for each of the scanning side driver circuit 42 and the image signal side driver circuit 43, so that a total of four clock signal lines are needed for external connection, which causes troublesome connecting operations.
In the on-board driver circuit composed of polycrystalline silicon semiconductor layers shown in FIG. 26, on the other hand, the characteristics of the thin-film transistors are far poorer than a driver circuit composed of single crystalline silicon, so that the power-supply voltage must be set at a higher level than in a MOSFET integrated circuit with single crystalline silicon. Consequently, the on-board driver circuit needs signal level conversion corresponding to the difference in power supply voltage when a signal is entered from an external circuit (MOSFET integrated circuit) composed of single crystalline silicon. For this, a level shifter circuit 100 is provided. However, the level shifter circuit 100 is made of thin-film transistors composed of polycrystalline silicon, so a normal phase and a reverse phase clock signal having no clock skew have a clock skew when passing the level shifter circuit 100. Thus, the fail phenomenon is caused when two-phase clock signals are entered, the same as when a single phase clock signal is entered, which makes it impossible to secure stable circuit operations of the shift registers.
In order to realize a smaller and thinner liquid crystal display panel, it has been considered to built a timing circuit on the same board as other units; however, it is impossible unless the fail phenomenon due to a clock skew is solved.
These problems are common to all motion circuits which are composed of polycrystalline silicon semiconductor layers and which have shift registers shifting start signals in time with a normal phase and a reverse phase clock signal.
In view of the above-mentioned problems, the object of the present invention is to provide a motion circuit which reduces the occurrence of the fail phenomenon due to the skew between a normal phase and a reverse phase clock signal for driving shift registers, thereby performing stable circuit operations with no malfunctions.
(1) In order to achieve the object, a first group of inventions comprises a clock skew reduction means for entering a normal phase clock signal and a reverse phase clock signal having a clock skew therebetween and for outputting a normal phase clock signal and a reverse phase clock signal having little clock skew therebetween to the shift register. The specific structure of the clock skew reduction means is realized by one of the following requirements (a)-(d) when a normal phase and reverse phase clock signals are generated from an entered single phase clock signal:(a) latch operations of the first and second latch circuits, (b) optimization of the transistor size of the first and second inverter chain circuits, (c) provision of a delay circuit on the reverse phase clock signal line side, or (d) provision of an inverter for each stage or for several stages of the shift register. As a result, a reduction in the skew between the normal phase and reverse phase clock signals secures stable operations of the shift register. Besides the shift register, the present invention is applicable to all kinds of logical circuits performing established operations by entering a normal phase and reverse phase clock signals.
A skew refers to the phase difference between a normal phase clock signal and a reverse phase clock signal.
The driver circuit having the structure (a) has the following effects. The first and second latch circuits entering a normal phase and reverse phase clock signals having a clock skew perform latch operations to be timed to make the normal phase and reverse phase clock signals have reverse polarities, and supply the latched signals to the respective shift registers as clock signals. As a result, the shift registers are each supplied with a normal phase and reverse phase clock signals having no skew.
The driver circuit having the structure (b) has the following effects. As for the first and second inverter chain circuits, there is a combination between an odd number of stages and an even number of stages that makes a minimum delay time of the inverter chain when the rate of increase in the transistor size between adjacent inverters is uniform. Therefore, the first and second inverter chain circuits are set to the combination of the odd number of stages and the even number of stages. As a result, when a single phase clock signal is entered to each of the first and second inverter chain circuits, the first and second inverter chain circuits output a normal phase and reverse phase clock signals having little skew.
The driver circuit having the structure (c) has the following effects. An entered single phase clock signal is reversed by the inverters to generate a reverse phase clock signal. The entered single phase clock signal is also sent to a delay circuit to be outputted as a normal phase lock signal. The delay circuit will delay the single phase clock signal by an established delay time so that there is no phase difference between the normal phase clock signal and the reverse phase clock signal. Consequently, the normal phase clock signal outputted from the delay circuit and the reverse phase clock signal outputted from the inverter should have little skew therebetween, which makes the shift register be supplied with these two clock signals having little skew.
The driver circuit having the structure (d) has the following effects. One inverter is provided for each stage or for a plurality of stages of the shift register in order to change either one of a normal phase and reverse phase clock signals into an opposite-phase clock signal. At that moment, the normal phase and reverse phase clock signals have the same length of skew as the delay time of the inverters; however, the load applied on the clock signal line is as small as one stage or several stages, so that the delay time of the inverters, or the clock skew is minimized.
(2) The second group of inventions provides the shift register with a means for increasing the maximum clock skew permitted by the shift register. The specific approaches to increasing the maximum permissible clock skew are as follows: (a) to increase time constant defined by the ON resistance of the first switching means and the input capacity of the second inverter, (b) to increase an rms value of the threshold voltage of the second inverter, and (c) to provide one delay circuit between each adjacent stages of the shift register. The maximum clock skew on each stage of the shift register (excluding the first stage having no fail phenomenon due to a clock skew) is increased to prevent the fail phenomenon, which secures stable operations of the shift register. Besides the shift register, the present invention is applicable to all logical circuits performing established operations with a normal phase and reverse phase clock signals.
The driver circuit having the structure (a) has the following effects. Increasing the time constant defined by the ON resistance of the first switching means and the input capacity of the second inverter decreases the increase rate of the input potential of the second inverter, which means an increase in the maximum clock skew on each stage of the shift register. Consequently, the input voltage of the second inverter fails to reach the threshold of the second inverter in the skew period, thereby preventing the occurrence of the fail phenomenon. The maximum permissible skew refers to the time required for the input potential of the second inverter to reach the threshold voltage of the second inverter.
The driver circuit having the structure (b) has the following effects. Even if the input potential of the second inverter increases, it fails to reach the threshold of the second inverter in a skew period because the threshold has a large effective value. This leads to the successful prevention of the occurrence of the fail phenomenon.
The driver circuit having the structure (c) has the following effects. Even if the input potential of the second inverter increases, it fails to reach the threshold of the second inverter in a skew period because the delay circuit provided between each adjacent stages of the shift register delays the input voltage starting to change. As a result, the occurrence of the fail phenomenon is successfully prevented.
(3) The application of the above-mentioned approaches (1) and (2) to an image signal side driver circuit and a scanning side driver circuit realizes a highly reliable on-board driver circuit for a liquid crystal display panel having no malfunctions due to the skew between a normal phase and reverse phase clock signals. Needless to say, the present invention is applicable to all motion circuits composed of polycrystalline silicon semiconductor layers as well as on-board driver circuits for a liquid crystal display panel.
(4) The effects of the first group of inventions and the second group of inventions are summarized as follows.
In a motion circuit composed of polycrystalline silicon semiconductor layers, and an on-board driver circuit for a liquid crystal display panel employing the motion circuit, the occurrence of the fail phenomenon due to the skew between a normal phase and reverse phase clock signals is prevented, which secures stable circuit operations with no malfunction. This allows the circuit to enter only a single phase clock signal from an external timing circuit, which reduces the number of connections with the external timing circuit. Furthermore, the absence of the fail phenomenon due to a clock skew allows the timing circuit to be an internal circuit, making a device or a liquid crystal panel provided with the motion circuit smaller and thinner in size.
The first and second group of inventions have their own effects as follows.
{circle around (1)} Effects of the First Group of Inventions
(a) In an on-board driver circuit for a liquid crystal display panel composed of polycrystalline silicon semiconductor layers, a normal phase and reverse phase clock signals generated inside the driver circuit by entering a single phase clock signal has a reduced skew therebetween, so that the shift register can operate in a stable manner with a small maximum permissible clock skew.
(b) The generation of the normal phase and reverse phase clock signals from an entered-single phase clock signal not only reduces the number of connection lines between the external timing circuit and the display panel, but also ensures compatibility with an external timing circuit for a conventional single crystalline silicon LSI.
(c) The structure of latching a clock signal by a specific signal can be applied to the low-speed clock signal of the scanning side shift register. The input/output signal of the image signal side shift register can be used as the specific signal instead of newly providing a latch pulse signal, so that the structure can be realized only by adding a simple circuit.
(d) The use of inverter chains has a simple circuit structure and allows the generation of the normal phase and reverse phase clock signals from an entered single phase clock signal. It also can be applied to the high-speed clock signal on the image signal side for its wide applicability.
(e) The generation of a reverse phase clock signal by the inverter provided for each stage or several stages not only allows the generation of the normal phase and reverse phase clock signals from an entered single phase clock signal, but also be realized only by adding a simple circuit. It also can be applied to the high-speed clock signal on the image signal side for its wide applicability.
{circle around (2)} Effects of the Second Group of Inventions
(a) Increasing time constant indicates increasing the clock skew of an entered clock permitted by a driver circuit itself (the maximum permissible clock skew). Consequently, stable operations of the driver circuit are secured even if a clock skew is somehow large, which improves the performance of the liquid crystal display panel containing the driver circuit.
Furthermore, the increase in time constant can be easily achieved by controlling the transistor size, which facilitates the control of the maximum permissible clock skew.
(b) Increasing the effective value of the threshold voltage of the second inverter has an effect of meeting the recent demand for making the threshold voltage of the transistor smaller, in addition to the above-mentioned effects of the second group of inventions.
(c) Disposing a delay circuit between each adjacent stages of the shift register has high control over the maximum permissible clock skew and high flexibility in design because an increase in the maximum permissible clock skew can be controlled by the number of delay circuits, in addition to the above-mentioned effects of the second group of inventions.